1. Field of the Invention
The present invention relates to a polysilicon thin film transistor having a bottom gate structure using copper and a method of making the same. More particularly, the present invention relates to a polysilicon thin film transistor having a trench type copper bottom gate structure and a method of making the same, in which copper with a low resistance value is used as a bottom gate by an electroplating method without using a copper patterning process so as to be appropriate for a large display, and a step coverage is solved by making a copper gate buried into and planarized in a trench structure.
2. Description of the Related Art
In general, various kinds of metal and metal alloys such as aluminum (Al), molybdenum (Mo), and molybdenum-tungsten (MoW) are used as a gate electrode constituting a bottom gate of a thin film transistor (hereinafter referred to TFT). The reason why the aluminum (Al), molybdenum (Mo), molybdenum-tungsten (MoW), etc., are used as a material of the gate electrode is because for example aluminum oxide (Al2O3) can be used as a gate insulation film to thereby make it easy to make the gate insulation film.
However, in the case that aluminum is used as a gate electrode material to implement a large display, in recent years, a resistance value of a gate line (GL) that is mutually connected with a gate electrode and is simultaneously formed with the gate electrode and that is simultaneously formed together with the gate electrode in general, or a data line (DL) that is orthogonally formed with respect to the gate line (GL) and is connected to a source region, is greatly increased in proportion to the dimension of a display, As a result, a gate signal and a data signal have been delayed and distorted.
Conventional gate electrode materials are metal materials including copper (Cu) whose resistance is smaller than that of aluminum (Al). However, an appropriate etching solution that is used for etching a copper film in order to form the gate electrode and gate line has not been developed. Further, there is a problem that an etching process for etching the copper film produces heavy metals causing an environmental pollution.
In addition, in the case that copper is used as the gate electrode in a large display, respective copper wires of one micrometer or more thick are required in order to make resistance of the copper wires sufficiently small. However, it takes long time of three hours or more to form a copper film of such a thickness using a typical deposition method. Further, in the case that a gate electrode structure of a thick film is employed, a gate insulation film that is directly formed on the upper portion of a gate electrode by a well-known process may cause a step coverage problem.
Meanwhile, a conventional technology of manufacturing an array substrate using copper as a gate electrode is disclosed in Korean Patent Laid-open Publication No. 10-2006-115522.
In the Korean Patent Laid-open Publication No. 10-2006-115522, signal wires and a thin film transistor are manufactured using an electroless plating method or an electroplating method whose deposition temperature is low, considering manufacturing temperature and stress act as big constraints in the case that the array substrate using copper as a gate electrode, in comparison with a case that a glass substrates is used at the time of production of signal wires such as gate lines and data lines and a thin film transistor in order to implement a flexible display device, to thereby prevent a flexible substrate from being bent or signal line layers from being cracked, and simultaneously to thereby promote a quality of display to be improved.
To this end, the Korean Patent Laid-open Publication No. 10-2006-115522 discloses that a first electrode layer made of nickel or molybdenum, a second electrode layer made of copper, and first and second line layers for use in gate lines and data lines are formed by the electroless plating method, to thereby form an electroplating seed layer, and then source and drain regions, and a third electrode layer and a third line layer for use in gate lines and data lines are formed by the electroplating method using the electroplating seed layer.
However, the method of forming the copper gate electrode and wires of the Korean Patent Laid-open Publication No. 10-2006-115522 includes a process of patterning first and second metal layers so as to form the copper gate electrode and wires using the electroplating method, after having formed the first electrode layer for enhanced adhesion and the second electrode layer made of copper on the entire surface of the substrate by the electroless plating. As a result, the Korean Patent Laid-open Publication No. 10-2006-115522 has the same problem as that of the conventional art at the time of etching the copper metal layer.
In addition, the technology disclosed in the Korean Patent Laid-open Publication No. 10-2006-115522 may cause a step coverage problem in a subsequent process of forming the gate electrode as a thick film of one micrometer or more thick, and does not present any related solutions.
Moreover, when source and drain regions are formed in alignment with a gate electrode in the conventional art, a mask for shielding ion implantation is formed on the upper portion of the gate electrode by using a separate exposure mask and then an ion implantation process is executed. Accordingly, an alignment error of 2 to 4 micrometers may be caused. Further, such an alignment error cannot be equally distributed to both ends of a channel region and leans toward one end of the channel region, to thereby become a factor of aggravating an electrical performance of the thin film transistor (TFT).